1. Field of the Invention
The present invention relates to a display control circuit which drives a display panel, and to a display device provided with the display control circuit.
2. Description of the Related Art
An active matrix-type liquid crystal display device is provided with, as liquid crystal drivers, multiple row drivers for driving row selection lines of a liquid crystal display panel, and multiple column drivers for driving column selection lines.
In the liquid crystal display device, a controller of the liquid crystal display panel transmits a data clock and gradation data indicating a gradation of an image to each of the multiple column drivers. Upon receipt of this, each of the column drivers loads the gradation data into an internal register at an edge of the data clock, converts the data into a gradation voltage, and then outputs the voltage to the corresponding column selection line.
In order to correctly load the gradation data into the register, it is necessary to have an ample time duration between an edge of the data clock and a change of the gradation data.
For this reason, conventionally, the phase relationship between the data clock and the gradation data has been adjusted in the controller of the liquid crystal display panel. In the row driver, a duty cycle of the received data clock has been kept equal to that in the transmitter side with use of a PLL.
On the other hand, recently, a screen size of a liquid crystal display panel has been increased, thereby increasing the lengths of wires for a data clock and gradation data from a controller to each column driver. Along this trend, the variation among wire lengths tends to become large. Thus, the variations among the wire capacities and wire resistances have been obviously seen. The variations among the wire capacities and wire resistances may increase a difference between a wiring delay time (delay time due to a wire length) of the data clock outputted to each column driver from the controller and that of the gradation data.
Due to the above-described difference in the wiring delay time between the data clock and the gradation data, the data clock and the gradation data has a phase difference when arriving at the row driver, even though the data clock and the gradation data have been transmitted after the phase adjustment in the controller. Such a phase difference is not eliminated even by adjusting the duty cycle of the data clock with the aforementioned PLL in the row driver. Accordingly, when loading the gradation data into a register, the row driver suffers from a shortage of the time duration between an edge of the data clock and a change of the gradation data.